The VLSI Design Testing Laboratory is designed to equip students with both theoretical knowledge and hands-on experience in the domain of Very Large-Scale Integration (VLSI) systems. Through a series of practical experiments, students will engage in designing, verifying, and testing a variety of VLSI circuits used in digital systems. These include applications such as ODD/EVEN parity generators, BCD-to-excess-3 code converters, and priority encoders. The lab also incorporates virtual simulations to help students build a strong foundation in both basic and advanced concepts of chip design and verification, thereby enhancing their comprehension of real-world VLSI applications.
The objective of the VLSI Design Testing Lab is to develop students' ability to analyze and evaluate the performance and reliability of VLSI circuits through systematic verification and fault-testing methodologies. Emphasis is placed on cultivating critical problem-solving skills related to identifying and troubleshooting faults in digital systems. Additionally, the lab aims to provide a strong conceptual and practical framework that supports students in understanding the complexities of real-world chip testing environments. This foundational expertise is essential for those aspiring to advance in the field of VLSI design and verification.
Associate Faculty,
Centre for system design, NITK SurathkalCentre for system design, NITK Surathkal
Associate Faculty,
Centre for system design, NITK Surathkal